ELEC3221 Digital IC and Systems Design

Module Overview

This module aims to provide a coherent introduction to digital VLSI design in CMOS, and to give students a broad understanding of the main principles required for system-on-chip design. Advanced techniques such as timing analysis and asynchronous design will also be introduced. In addition, the module extensively covers hardware architectures and timing behaviours of fundamental computer arithmetic ciruits.

Aims & Objectives

Aims

Knowledge and Understanding

Having successfully completed this module, you will be able to demonstrate knowledge and understanding of:

The Principles of CMOS Digital Circuits
Power-reduction Techniques

Subject Specific Intellectual

Having successfully completed this module, you will be able to:

Describe the principles of asynchronous circuits
Analyse the performance of synchronous systems
Describe architectures for Arithmetic Datapath Blocks

Subject Specific Practical

Having successfully completed this module, you will be able to:

Design and layout simple digital CMOS logic gates

Syllabus

Introduction to IC Design

IC system design options
CMOS processing, layout and design rules
Stick diagrams
Static complementary gates
System design using standard cells

Timing Schemes in Digital Systems

Principles of Synchronous Design
Clock trees and clock management
Asynchronous Circuits
Design and implementation of Synchronisers
Metastability in Digital System

Design of large digital Systems

Fundamental concepts of datapath and controller
Circuit Power Consumption, design tradeoffs speed-power, introduction to low power circuit design
Design hierarchy

Architecture of Arithmetic Datapath Blocks (Adders and Multipliers)

Comparision of standard designs
Complexity analysis
Delay analysis

Learning & Teaching

Learning & teaching methods

Activity	Description	Hours
Lecture	One double lecture slot and one single lecture slot per week.	36
Tutorial	one single lecture slot per week	12

Assessment

Assessment methods

Method	Hours	Percentage contribution
L-Edit Gate Design	-	10%
Exam	2 hours	90%

Referral Method: By examination, with the original coursework mark being carried forward

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