Digital System Design with VHDL goes global

A new edition of a student textbook, Digital System Design with VHDL, by ECS academic Professor Mark Zwolinski, has just been translated into four languages.

Published by Pearson Education, the book develops the idea of combining a text on digital design with one on VHDL.

VHDL is one of the two main hardware description languages used to design digital systems. Professor Zwolinski is writing a new version of the book to cover the latest version of the other language, SystemVerilog, to be published in 2009.

'When the first edition of this book was published, the idea of combining a text on digital design with one on VHDL seemed novel,' said Professor Zwolinski. 'The book has now been adopted by several universities as a core text.'

'Digital System Design with VHDL' is intended as a student textbook for both undergraduate and postgraduate students.

'It has often been assumed that topics such as VHDL are too specialized for second year teaching and are best left to final year or postgraduate courses,' said Professor Zwolinski. 'There are several good reasons why VHDL should be introduced earlier into the curriculum. With increasing integrated circuit complexity, industry needs graduates with knowledge of VHDL and the associated design tools. If left to the final year, there is little or no time for the student to apply such knowledge in project work.'

'Digital System Design with VHDL' has now been translated into Polish, Chinese, Japanese and Italian.