Date:

2008-2010

Themes:

Modelling and Simulation, Environmental modelling, Condition monitoring

The insulation used for a high voltage application is one of the most important components in any design because breakdown of the insulation may cause total failure of the whole component. The electrical insulation system is subjected to high electrical, mechanical and thermal stresses which can age and degrade the insulation to the point where partial discharges (PD) can become a regular occurrence ultimately leading to total breakdown. Detection and analysis of PD activity is therefore important to ensure the health and lifetime of any high voltage asset.

Partial discharge is a discharge event that does not bridge the electrodes within an electrical insulation system under high voltage stress. In high voltage components, the measurement of partial discharge is used in the performance assessment of an insulation system. Through modelling and measuring the discharge process a better understanding of the phenomena may be attained. This project describes the development of a mathematical model describing partial discharge in a spherical cavity and ellipsoidal cavity within a homogeneous dielectric. The model developed is used to study the influence of the applied frequency on partial discharge activity and also the influence of the cavity size and cavity location within the insulation material on partial discharge frequency dependent activity. The simulation results can then be used within insulation diagnostics to assist in the assessment of the performance of the insulation system.

Primary investigators

• George Chen
• Paul Lewin

Secondary investigator

• hai07r

Associated research group

• Electronics and Computer Science

Date:

2008-2011

Themes:

Assessment, Technology Enhanced Learning, Accessible Technologies

Funding:

JISC

A number of technical and policy issues are of concern within the University around e-assessment, including:

• an increasing need for interoperability;
• migration from legacy systems;
• quality assurance through item and test statistics;
• AER (additional educational requirements) and accessibility issues;
• provision of mathematical notation in science and engineering questions; and, most importantly,
• student and staff engagement with the relevant technologies (such as Web 2.0 and mobile devices) and services.

The University has received funding to accelerate the process of both implementing an open source, service based solution to institutional e-assessment and addressing institutional change by engaging academics and students in co-design and co-deployment. In line with the recently introduced University e-Learning Enhancement Strategy, which places the quality of student learning as its first objective, the EASiHE project intends to provide an open source solution for formative assessment by integrating services currently available within the JISC eFramework.

The project will:

• take the JISC-funded ‘EdSpace’ repository and elements of the ‘Faroes’ project to provide ‘Web 2.0’ content and services to users;
• incorporate the IMS Question and Test interoperability standard by integrating the ‘AsDel’ assessment delivery engine, integrating the ‘MathQTI’ standard, and providing QTI migration services sourced from the ‘MCQFM’ project;
• ensure the system is informed by the ‘LexDis’ project for accessibility;
• include relevant lessons from the ‘mPLAT’ and ‘Remora’ projects in providing for mobile learning and assessment; and
• incorporate a relatively underutilised and ‘new’ form of assessment, peer assessment, based upon the ‘Peer Pigeon’ project.

The main deliverables include:

• the provision of an open source e-assessment repository;
• services for the contribution and migration of assessment questions, tests, and peer assessments;
• services for the delivery of tests and peer assessments;
• documentation supporting the pedagogical design of e-assessments at higher levels of Bloom’s taxonomy; and
• dissemination material for the wider sector dealing with institutional change using the processes of co-design and co-deployment.

As partners in the JISC Institutional Innovation Support Project, EASiHE will be actively involved in producing briefing materials and training activities for exemplary practice.

Primary investigators

• Gary Wills
• Dr Bill Warburton, iSolutions
• Lester Gilbert

Secondary investigator

• pz2g12

Associated research group

• Electronic and Software Systems

Date:

2008-

Theme:

Communication and Networking

The aim of this research is to beneficially redistribute energy consumption in wireless sensor networks. Typically, sensor nodes have scarce energy resources and must rely on energy harvesting to prolong their life. By contrast, the sink node is often integrated into a higher-level system and can benefit from the accompanying plentiful energy resources, such as the mains. It is therefore desirable to redistribute energy consumption from the sensor nodes to the sink node. This can be achieved using iterative decoding.

Primary investigator

• Robert Maunder

Secondary investigators

• Geoff Merrett
• asw05r
• Bashir Al-Hashimi
• Lajos Hanzo

Associated research groups

• Pervasive Systems Centre
• Communications Research Group
• Electronic Systems and Devices Group
• Electronics and Electrical Engineering

Date:

2006-

Themes:

Healthcare, Healthcare in ECS, Wireless Sensing and Sensor Networks

This project is investigating the development and demonstration of a pervasive home welfare monitoring system. The system aims to use unobtrusive sensors for early detection and automated reporting of deteriorating physiological health parameters and enabling independent living.

Primary investigator

• sjs05r

Secondary investigators

• Bashir Al-Hashimi
• Nick Harris
• David De Roure

Associated research groups

• Pervasive Systems Centre
• Electronic Systems and Devices Group
• Electronics and Electrical Engineering

Date:

2006-

Theme:

Environmental Monitoring

To develop algorithms and protocols that can improve the scalability of sensor networks by using cluster-based routing mechanisms. The network must be able to balance energy consumption between nodes and maintain message latency under predetermined values.

Primary investigator

• pneb06r

Secondary investigators

• Nick Harris
• Neil White

Associated research groups

• Electronic Systems and Devices Group
• Electronics and Electrical Engineering

Date:

2007-

Themes:

Healthcare, Healthcare in ECS, Wireless Sensing and Sensor Networks

The group intends to develop a Long-term Patient Monitoring Research Platform to support and assist health-care providers. The Research platform, which does not intend to rely on a central server or a continuously connected Internet connection, aims to act as a low-cost support tool to aid health-care providers of the future.

Primary investigator

• ddj07r

Secondary investigators

• jsr
• Nick Harris

Associated research groups

• Electronic Systems and Devices Group
• Electronics and Electrical Engineering

Date:

2003-2007

Theme:

Nanoelectronics

The continued scaling of MOSFETs to the deca-nanometre regime has reached the point where the transistor size is now comparable with the grain size in a polysilicon film (typically 100-200nm). The time is therefore right to research processing techniques that would allow a transistor to be fabricated inside a grain of polysilicon. Such transistors would be expected to have significantly better performance than thin film transistors (TFTs) because grain boundaries would be eliminated from the channel region. The transistor performance might also approach that achievable in single-crystal silicon if good control could be obtained over the quality of the silicon inside the polysilicon grain. The applications for transistor-in-a-grain technology would potentially be enormous, and would include high-performance large area electronics, displays and any technology where low temperature processing was required. In the longer term, this technology may also be attractive for post-scaling CMOS, since it would enable 3D CMOS technologies to be implemented.

Layers of polycrystalline silicon self-assemble during growth and hence the positions of the grains and grain boundaries are random. The key issue in researching transistor-in-a-grain technology is therefore to devise processing techniques that allow the polysilicon grains to be precisely located with respect to the position of the transistor. This thesis investigates grain localization techniques and transistor architectures for transistor-in-grain technology. Two novel methods of low temperature crystallization of amorphous silicon are researched to increase the grain size and controlling the grain boundary locations. One method uses fluorine during metal induced lateral crystallization (MILC) of α-Si, which suppresses random grain nucleation during crystallization anneal and increases the laterally crystallized distance. Fluorine implantation also significantly reduces the density of the nickel-silicide precipitates and improves the grain texture in the laterally crystallized silicon. Another method employs germanium seed where a new amorphous silicon crystallization phenomenon has been identified to originate from the perimeter of the germanium seed during low temperature anneal and grain localization is achieved without any metal contamination. These methods of devising high quality poly-silicon layer have considerable commercial potential for a number of devices like thin film transistors for large area electronics, transistor-in-grain for 3D CMOS, thin film solar cells, sensor applications in a cost effective thin film based nanowire technology and any devices where low temperature processing is required.

Primary investigator

• Peter Ashburn

Secondary investigator

• mmah

Associated research groups

• Nano Research Group
• Southampton Nanofabrication Centre

Date:

2007-2010

Theme:

Nanoelectronics

Funding:

EPSRC

This research aims to investigate the use of CMOS-compatible vertical MOSFETs for the implementation of medium-power RF circuits, opening the way to higher integration of RF systems. Vertical transistors are currently of interest because they offer an alternative route to ultra-short channel MOS transistors with relaxed lithography requirements (and hence considerably lower costs), decouple gate length from the packing density and provide improved current drive per unit silicon area compared with conventional lateral CMOS. In this research approaches will be investigated that deliver these benefits through the integration of vertical MOSFETs in a mature CMOS technology with minimum additional masks above those required for standard 0.5 micron CMOS. The intention is to appraise in depth, the feasibility of this novel technology for the manufacture of low-cost RF solutions.

The challenges of vertical MOSFETs for RF applications are high overlap capacitance, short channel effects, susceptibility to dry etch damage and the lack of an appropriate silicidation technology. A detail investigation has been done to deliver solutions for challenges like overlap capacitance, short channel effects and dry etch damage. CMOS compatible Fillet Local Oxidation (FILOX) process, novel structures (frame gate) and optimised process have been researched to reduce the overlap capacitance and to eliminate dry etch damage associated device degradation. The resulting transistors are found to have significantly improved immunity to short channel effects, with near ideal sub-threshold slopes of 70 to 80 mV/decade, and DIBL of 30 to 35 mV/V. Most recently we have developed for the first time a silicidation technology for surround gate vertical MOSFETs. The technology uses a double spacer comprising a polysilicon spacer for the surround gate and a nitride spacer for the silicidation. For a 120 nm channel length, silicided frame gate vertical nMOSFETs show a 30% improvement in the drive current with an excellent sub-threshold slope of 78mV/decade and a DIBL of 30 mV/V. For an 80 nm channel length, a 43% improvement in the drive current is obtained. Vertical transistors with our FILOX process and silicidation resulted in a transistor with low overlap capacitance and high transistor transconductance. While conventional planar nMOS devices exhibit a fT of 10 GHZ in a 0.5 micron technology node, our vertical nMOS devices fabricated by above mentioned FILOX and silicidation process demonstrating a fT of 20 GHZ in the same technology node. We are currently investigating several RF circuits with verical nMOS devices aimed at the highly lucrative 1-10 GHz market.

Primary investigators

• Peter Ashburn
• Steve Hall
• Bill Redman-White
• Octavian Buiu

Secondary investigator

• mmah

Partner

• University of Liverpool

Associated research groups

• Nano Research Group
• Southampton Nanofabrication Centre

Date:

2007-

Theme:

Algorithms for Wireless Sensor Networks

One of the directions that Wireless Sensor Networks are considered to play an important role, is in motion detection and target tracking systems. This research focuses on employing l ow-cost,low-power, limited sized devices, for detection and tracking of mobile targets. Novel tracking algorithms and information processing techniques are investigated to improve performance. This project aims at developing a system capable of handling multiple targets moving arbitrarily in the networks coverage area.

Primary investigator

• ebm07r

Secondary investigators

• jsr
• Neil White

Associated research groups

• Electronic Systems and Devices Group
• Electronics and Electrical Engineering

Date:

2005-

Themes:

Energy Harvesting & Sensing Devices, Low-Energy Sustainable Systems, Low-Energy Sustainable Systems

To develop and demonstrate an integrated approach to power management such that sensors within a sensor network are able to manage their energy requirements, and harvest energy from the local environment, whilst simultaneously coordinating their activities in order to achieve system-wide aggregate goals.

Primary investigators

• asw05r
• Neil Jonathan Grabham
• Nick Harris
• Neil White

Associated research groups

• Electronic Systems and Devices Group
• Electronics and Electrical Engineering